Article ID: 000077028 Content Type: Troubleshooting Last Reviewed: 03/08/2023

Why does the csr_sysref_singledet bit get cleared unexpectedly before SYSREF is toggled from low to high when using the JESD204B Intel® FPGA IP at data rates greater than 16 Gbps in Intel Agilex® 7 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • JESD204B Intel® FPGA IP
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.3 and earlier, when using the JESD204B Intel® FPGA IP in Subclass mode 1 AND at 16 Gbps < data rate <= 19.2 Gbps you might see the issue described below when using the Intel Agilex® 7 devices.

    After the JESD204B Intel® FPGA IP has sampled SYSREF for the first time and cleared the CSR bit csr_sysref_singledet to 0, when this CSR bit is subsequently set by the user to a value of 1 to sample another SYSREF edge, it gets cleared immediately even before the SYSREF is toggled from low to high. This is caused by an internal signal that clears the csr_sysref_singledet being stuck at 1 for data rates greater than 16 Gbps.

    Resolution

    This issue can only be recovered by applying txlink_rst_n or rxlink_rst_n.

    A patch can be provided upon request through Intel® Premier Support (IPS).

    This problem is fixed starting from the Intel® Quartus® Prime Pro Edition Software version 20.4.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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