Article ID: 000077025 Content Type: Troubleshooting Last Reviewed: 09/14/2020

When using the E-Tile Hard IP for Ethernet Intel® FPGA IP 10G/25G PTP variants does the Timing Analyzer report o_sclk signal as an unconstrained clock?

Environment

  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 DX FPGA
  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
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    Critical Issue

    Description

    When using the E-Tile Hard IP for Ethernet Intel® FPGA IP 10G/25G PTP variants , the o_sclk signal is an asynchronous pulse routed through clock network. Timing Analyzer incorrectly identifies the o_sclk signal as a clock source and reports it as an unconstrained clock.

    Resolution

    No workaround is required, you can safely ignore this Timing Analyzer analysis of o_sclk as an unconstrained clock.

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