Article ID: 000077023 Content Type: Troubleshooting Last Reviewed: 06/17/2020

Is the supported range for Control Bits (CS) in the JESD204C Intel® FPGA IP correct?

Environment

    Intel® Quartus® Prime Pro Edition
    JESD
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Description

Due to a known problem in Intel® Quartus® Prime Pro software version 19.4 and earlier, the JESD204C Intel® FPGA IP has a Control Bits (CS) range of 0 - 31. However the supported range is 0 - 3. 

Resolution

Select Control Bits (CS) within 0 - 3 range when using the JESD204C Intel® FPGA IP. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.

Related Products

This article applies to 4 products

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 TX FPGA

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