Due to a bug in the Quartus® II software version 13.0 and earlier, you may see transceiver PMA functionality problems when using NIOS II as an Avalon Memory Mapped Master for the reconfiguration controller when using Stratix® V, Arria® V, or Cyclone® V transceiver devices.
When accessing the following transceiver PMA functions through the reconfiguration controller Avalon memory mapped interface using a NIOS II master or other Avalon master you may encounter a failure in the transceiver PMA.
|Stratix V GX/GT/GS, Arria V GZ||Arria V GX/GT/ST/SX||Cyclone V GX/GT/ST|
|Pre and post CDR reverse serial loopback||Pre and post CDR reverse serial loopback||Pre and post CDR reverse serial loopback|
|-||Rx equalization||Rx equalization|
The PMA failure is caused by corruption inside the reconfiguration controller if the reconfig_mgmt_address bus toggles when the reconfig_busy signal is asserted. The failure can be recovered by reprogramming the FPGA.
To work around the problem, you can insert logic that prevents toggling of the reconfiguration controller reconfig_mgmt_address bus when the reconfig_busy signal is asserted.
Or you can replace the "alt_xreconf_uif.sv" file that resides in your Reconfiguration Controller Megawizard™ generated <instance_name> folder with this file and recompile your design.
This problem will be fixed in a future version of the Quartus II software.