How do I compile the Programming Language Interface (PLI), convert_hex2ver.c, in ModelTech to simulate MAX PLUS® II output files for designs containing ROM or initialized RAM?

Download the convert_hex2ver.c file from the EDIF web site (http://www.edif.org/lpmweb/convert_hex2ver.c).

• Create a file called veriuser_mti.c with the following contents:

  #include "veriuser.h"
  #include "acc_user.h"
  
  extern convert_hex2ver();
  
  s_tfcell veriusertfs[] =
  {
      /*** Template for an entry:
      { usertask|userfunction, data,
        checktf(), sizetf(), calltf(), misctf(),
        ""},
      Example:
      { usertask, 0, check, 0, func, misctf, "" },
      ***/
  
      /*** add customer task entries here ***/
      /* This converts intel binary bit patterns to a verilog readmemb format*/
      {usertask, 0, 0, 0, convert_hex2ver,   0,  "",  1},
      
  {0} /*** final entry must be 0 ***/
  };
  
  /* mti interface */
  void init_usertfs()
  {
   p_tfcell usertf;
   for (usertf = veriusertfs; usertf; usertf  ) {
    if(usertf->type == 0)
      return;
    mti_RegisterUserTF(usertf);
   }
  }
  

• Compile and link the two C source files (veriuser_mti.c and convert_hex2ver.c). For example:

   

  gcc -c -I/<full_path_to_modelsim>/include convert_hex2ver.c
gcc -c -I/<full_path_to_modelsim>/include veriuser_mti.c
ld -G -o altera.sl convert_hex2ver.o veriuser_mti.o

• Create and edit a local copy of modelsim.ini to include the following information:

   

  Veriuser = /<full_path_to_where_you_created_altera.sl>/altera.sl

• Compile the Verilog Source file using the vlog command. You should see the following messages while analyzing the file using vlog:

  Loading work.<design_name> Loading /<full_path_to_where_you_created_altera.sl>/altera.sl

• Proceed with simulation.