Article ID: 000076996 Content Type: Product Information & Documentation Last Reviewed: 02/14/2023

How should the CKE signal be terminated for DDR3 and DDR4 interfaces?

Environment

    Intel® Quartus® Prime Design Software
    External Memory Interfaces Intel® Arria® 10 FPGA IP
    External Memory Interfaces Intel® Stratix® 10 FPGA IP
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Description

The CKE signal is pulled down to GND on the DDR3 HiLo daughter card and terminated with a Thevenin parallel termination on the DDR4 HiLo daughter card.

Resolution

All address and command signals, including the CKE signal, should use a fly-by termination for Arria®10 and Stratix®10 DDR3 and DDR4 interfaces.

These signals should be terminated with a resistor to VTT at the end of the fly-by topology. This termination is required only for discrete memory device implementations and is not required for DIMMs. 

Related Products

This article applies to 2 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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