Article ID: 000076961 Content Type: Troubleshooting Last Reviewed: 08/08/2023

Can the Intel® Stratix® 10 HBM2 efficiency monitor test pattern run in an infinite loop?

Environment

Bug ID: 1508184108

Quartus Edition

Intel® Quartus® Prime Pro Edition

Version Found: 19.1

FPGA Intellectual Property

External Memory Interfaces Intel® Stratix® 10 FPGA IP

Version Found: 19.1

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Description

The efficiency monitor test pattern is implemented to run only one loop regardless of the traffic generator parameter setting.

Resolution

To make the test pattern run continuously, toggle the wmcrst_n_in signal after the traffic_gen_pass signal is asserted high.

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