Article ID: 000076961 Content Type: Troubleshooting Last Reviewed: 07/21/2020

Can the Intel® Stratix® 10 HBM2 efficiency monitor test pattern run in an infinite loop?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The efficiency monitor test pattern is implemented to run only one loop regardless of the traffic generator parameter setting.

     

    Resolution

    To make the test pattern run continuously, toggle the wmcrst_n_in signal after the traffic_gen_pass signal is asserted high.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA

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