Article ID: 000076960 Content Type: Product Information & Documentation Last Reviewed: 10/06/2020

How does the transaction count operate after grant moves to the next master when using the Intel® Stratix®10 MX HBM2 controller with the AXI* Switch?

Environment

    Intel® Quartus® Prime Pro Edition
    External Memory Interfaces Intel® Stratix® 10 FPGA IP
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Description

When a master is not ready to issue the expected total transaction, grant will go to the next master, and the transaction counts will be refreshed to the original transaction counts.

Related Products

This article applies to 1 products

Intel® Stratix® 10 MX FPGA

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