Article ID: 000076958 Content Type: Error Messages Last Reviewed: 08/21/2023

Error(175001): The Fitter cannot place 1 pin, which is within <esram_name>

Environment

  • Intel® Quartus® Prime Pro Edition
  • eSRAM Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see this error message when compiling a project which instantiates the Intel® eSRAM IP followed by information messages similar to these referring to the input ref clock :

    Error(175001): The Fitter cannot place 1 pin, which is within <esram_name>

    Info(14596): Information about the failing component(s):

    Info(175028): The pin name(s): <esram_refclk_name>

    The reason this fitter error occurs is that the eSRAM input PLL reference clock does not have an LVDS I/O standard assignment in the project.

    Resolution

    The eSRAM input PLL reference clock only supports the LVDS I/O standard but the Intel® eSRAM IP itself does not include this assignment.

    Add an LVDS I/O standard qsf assignment for the eSRAM PLL reference clock and place it on the dedicated input clock pins (CLK_ESRAM_[0,1]p/n) on the top or bottom edge of the FPGA.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA