Article ID: 000076957 Content Type: Troubleshooting Last Reviewed: 02/28/2019

Reference clock network for 12 tiles is not currently supported


  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP

    A fitter error with a message similar to this may be seen when using the Intel® Stratix® 10 EMIF IP if there are PLL reference clock connections spanning across more than 8 I/O banks :

    Internal Error: Sub-system: CPLL, File: /quartus/periph/cpll/refclk_gen6_param_util.cpp, Line: 387

    Reference clock network for 12 tiles is not currently supported!

    This is typically seen on larger Intel Stratix 10 devices with multiple external memory interfaces placed in an I/O column sharing core clocks or the PLL reference clock. Note that when sharing core clocks, the PLL reference clock is also distributed in the core clocks sharing bus that connects between the core clock master and slaves.


    Make sure that the EMIF PLL reference clock is not connected to more than 8 adjacent I/O banks in the same I/O column. For information about the I/O banks of your Intel® Stratix® 10 device, refer to the Intel Stratix 10 Device Pin-Out Files.  

    In the table on the first page of the pinout document, it shows the I/O banks which are bonded out with the number of pins for each I/O bank for each supported package. For the determination of the 8 I/O banks for the PLL reference clock path, this also includes I/O banks which are not bonded out and are indicated with a "-" in the table.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs



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