Seriallite III MegaCores version 13.1 and older need to use an internal clock to synchronize the crc_error_inject input signal. The following figure shows the workaround for this issue.
The user needs to route the internal clock, “tx_coreclkin” to the top level module by creating output ports up the hierarchy. In the user’s top level design, the “tx_coreclkin” clock can then be used to drive the “crc_error_inject” input signal.
Assuming a Seriallite III instance name of “sl3” and a user’s top level design as top, the following are the steps to implement the above solution.