Article ID: 000076956 Content Type: Troubleshooting Last Reviewed: 02/16/2016

Seriallite III has timing violations on two unrelated clocks for crc_error_inject input signal


  • Quartus® II Subscription Edition
    Description Serialite III MegaCore versions 13.1 and earlier may show timing violations in TimeQuest between two different clocks. The timing violations involve the input signal, crc_error_inject. The Seriallite III User Guide instructs the user to use the "tx_user_clock" to drive the "crc_error_inject" signal. Because the crc_error_inject signal is not synchronized to the correct clock inside the Seriallite III core, timing violations are flagged.

    Seriallite III MegaCores version 13.1 and older need to use an internal clock to synchronize the crc_error_inject input signal.  The following figure shows the workaround for this issue.

    Figure 1.

    The user needs to route the internal clock, “tx_coreclkin” to the top level module by creating output ports up the hierarchy.  In the user’s top level design, the “tx_coreclkin” clock can then be used to drive the “crc_error_inject” input signal.

    Assuming a Seriallite III instance name of “sl3” and a user’s top level design as top, the following are the steps to implement the above solution.

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