Article ID: 000076946 Content Type: Troubleshooting Last Reviewed: 04/05/2017

Why does the RapidIO II auto-generated VHDL simulation testbench fail to compile in certain configurations of the RapidIO II IP core?

Environment

    Intel® Quartus® Prime Pro Edition
    RapidIO II (IDLE2 up to 6.25 Gbaud) Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

In some configurations of the RapidIO® II IP core, generated VHDL simulation will encounter compilation error where a port is missing in the entity instantiating another entity.
 
Example Error in ModelSim® simulator.

Port "<port_name>" of entity "<entity name>" is not in the component being instantiated.

​This error is only found in variations where the I/O Master, I/O Slave, Doorbell, Maintenance or Pass-through modules are disabled.

Verilog version is not impacted.

Resolution

Use Verilog version of the simulation testbench.

Related Products

This article applies to 7 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Arria® V GT FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Cyclone® V FPGAs and SoC FPGAs
Stratix® V FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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