Article ID: 000076942 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is the 10G Ethernet MAC avalon_st_tx_ready signal de-asserted for at least two clock cycles for each packet streaming?

Environment

    Ethernet
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The avalon_st_tx_ready signal will be de-asserted for at least two clock cycles for every new packet received on the Avalon® -ST streaming interface. This is necessary for the MAC to perform the following functionality:
• Insert preamble and SFD
• Insert padding if the frame is short frame.
• Insert CRC
• Insert End of Frame Delimiter
• Insert the right inter packet gap

This does not affect the 10G Ethernet MAC throughput.

Resolution No workaround or fix is available.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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