Internal Error Occur When Simulating the JESD204B IP Core VHDL Simulation Model using VCS MX

When you use the VCS MX simulation tool to simulate the VHDL simulation model of the JESD204B IP core, you will encounter an error message shown below:

Error-[INTERR] Internal Error Encountered an internal error that can only be remedied through VCS customer support. Please send the following internal error string to VCS customer support: \'Cannot extract thunk\'

This issue affects the JESD204B IP core in Quartus II software versions 14.0 Arria 10, 14.1, 15.0, and 15.1.

Set XLRM=TRUE in the synopsys_sim.setup file.