Critical Issue
Description
The post-compile timing script reports the following error:
‘Couldn't find the clock output pins. Stop.’
This issue affects designs using the DDR SDRAM controller, when the PLL counters have been reordered or the clocks for the DDR SDRAM interface are not on global clocks. This issue may occur automatically in the Fitter if there is pressure on global clock resources.
The design fails.
Resolution
Make the following two assignments:
ddr_pll_stratixii:g_stratixpll_ddr_pll_inst Preserve
PLL Counter Order On
ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk3*
Global Signal Global Clock
Replace the file names of the PLL with those in your DDR SDRAM controller design.
This issue will be fixed in a future version of the DDR and DDR2 SDRAM Controller Compiler.