Article ID: 000076909 Content Type: Troubleshooting Last Reviewed: 01/18/2023

Why is there a mismatch on the write and read data between the AXI bus interface and the Intel® Stratix® 10 MX HBM2 simulation model messages during simulation?

Environment

    Intel® Quartus® Prime Pro Edition
    External Memory Interfaces Intel® Stratix® 10 FPGA IP
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Description

The mismatch occurs because the write data from the AXI bus interface goes into the Intel® Stratix® 10 MX HBM2 IP's soft adapter and through the Universal Interface Block Subsystem before it reaches the Intel® Stratix® 10 MX HBM2 memory model.

Resolution

The "write data" bus value reported in the HBM2 memory model has been modified due to the data bus inversion (DBI).

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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