Description
The top-level receive and transmit lanes of transceivers may appear to be single lanes in Qsys, but once the Qsys interconnect is generated the HDL top-level output will reflect the multi-lane width.
Other transceiver I/O such as tx_clkout relfect multi-lane / bonded assignments and change within Qsys to display additional lanes such as tx_clkout0, tx_clkout1, and so on. These I/O are reflected within Qsys so they are available to the Qsys interconnect. However, the top-level serial lines are normally exported from Qsys as conduits, so they may appear to be single lane rather than additional lanes such as rx_serial_data_0, rx_serial_data_1, and so on.