Article ID: 000076880 Content Type: Troubleshooting Last Reviewed: 10/25/2017

Why do I see elaboration time errors when simulating Intel Stratix 10 designs in Aldec Riviera-PRO 2017.02?

Environment

    Intel® Quartus® Prime Pro Edition
    Simulation, Debug and Verification
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Critical Issue

Description

Due to a bug in Aldec Riviera-PRO* 2017.02, you may see elaboration time errors similar to the line below when simulating Intel® Stratix® 10 designs.

# KERNEL: ERROR: The attributes for bit 'cr_rlpbk_en' have illegal conflicting values

Resolution

Contact Aldec for a later version of Riviera-PRO with a fix for this problem.

Related Products

This article applies to 1 products

Intel® Stratix® 10 GX FPGA

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