Article ID: 000076878 Content Type: Troubleshooting Last Reviewed: 10/09/2017

Why does simulation fail when using the Interlaken design example?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interlaken (2nd Generation) Intel® FPGA IP
  • Interlaken
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Interlaken IP Core (2nd Generation), the rx_digitalreset and reset_stat keep toggling when using the modelsim or ncsim simulation environment. As a result, the simulating system can't enter lock status or finish successfully.

    Resolution

    This problem does not exist when using the VCS simulation environment.

    This problem has been fixed starting in version v17.1 of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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