Article ID: 000076877 Content Type: Troubleshooting Last Reviewed: 10/22/2020

Why is the 25G Ethernet Intel® FPGA IP oversized frame error not asserted when frame length setting is greater than 32k?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • 25G Ethernet Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Edition software version 18.1 and later, the 25G Ethernet Intel® FPGA IP core MAC frame length internal counter will overflow when frame length configuration register "MAX_TX_SIZE_CONFIG" and "MAX_RX_SIZE_CONFIG" is set to greater than 32k value.

    Oversized frame error stays de-asserted as internal counter already overflow, hence not reflecting the actual error in hardware. 

    Resolution

    This problem is fixed starting from the Intel® Quartus® Prime Pro Edition v20.3 software onwards.

    The 25G Ethernet Intel® FPGA IP core MAC design fixed detail as below:

    • To handle frame length equal to MAX_TX_SIZE_CONFIG and MAX_RX_SIZE_CONFIG of 64k moving forwards.
    • Also if Ethernet packet frames with a size larger than 64k is received in the 25G Ethernet Intel® FPGA IP core, the MAC will detect the overflow condition and stops incrementing the internal frame length counter. Oversized frame error will also get asserted to indicate an overflow scenario.

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