Article ID: 000076870 Content Type: Troubleshooting Last Reviewed: 10/23/2019

Why does the Intel® Stratix® 10 L/H-Tile PCIe* Endpoint's Transaction Layer get stuck in reset when Function-Level Reset FLR is initiated?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    When Function-Level Reset (FLR) capability is disabled, a Configuration Write setting the Device Control Register's parameter Initiate Function-Level Reset to 1 will cause the Intel® Stratix® 10 L/H-Tile PCIe* Endpoint's Transaction Layer to be stuck in reset.

    The Intel® Stratix® 10 L/H-Tile PCIe* Endpoint will respond to subsequent requests with Unsupported Request (UR) TLP.

    Conventional reset is needed to recover from this error case, e.g. PERST#, Hot Reset or Link Disable/Enable.

    Resolution

    To work around this problem, enable FLR capability in the IP Parameter Editor.

     

    The FLR capability has been enabled by default starting with the Intel® Quartus® Prime Pro edition software version 19.3. 

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