Article ID: 000076869 Content Type: Troubleshooting Last Reviewed: 07/08/2019

Why do I see Hold timing violations in Intel® Agilex™ devices when using PAM4 varients of the Interlaken IP Core (2nd Generation) Intel® FPGA IP.

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interlaken (2nd Generation) Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the PAM4 implementation of the Interlaken IP Core (2nd Generation) Intel® FPGA IP, hold time timing closure violations may be seen in Intel® Agilex™ devices in Intel® Quartus® Prime Pro Edition v19.2 software.

    Resolution

    A possible temporary work around for this timing problem is to run seed sweeps so that better timing results are found.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.