Article ID: 000076858 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What load capacitance should I use in I/O timing analysis of Stratix II and Cyclone II devices?



Versions of the Quartus II software released before version 4.1 used predefined non-zero load capacitance for timing analysis (for example, a 10 pF load for LVTTL output). Those predefined capacitance values did not include possible board structure and receiver loads, therefore the timing analysis was less accurate than if actual loading was specified to Quartus II software.

In the Quartus II software version 4.1, Stratix II and Cyclone II devices use new timing models with a default load of 0 pF for each I/O standard except for PCI and PCI-X (both 10 pF). The output pin loading only affects clock to output (tCO) timing and not I/O performance. Simulate board delay time for your design including board structure and receiver loads. If you do not wish to simulate for timing, the Quartus II software version 4.1 provides delay adders for different capacitive loads at different I/O standards. The output loading can be specified in Quartus II software using the "Output Pin Loading" logic option.

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Stratix® II FPGAs



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