Article ID: 000076852 Content Type: Troubleshooting Last Reviewed: 06/29/2017

Why is the parameter “Use core PLL reference clock connection” not available in the PHYLite IP Parameter Editor?

Environment

    Intel® Quartus® Prime Pro Edition
    PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Starting with the Quartus® Prime software version 17.0, the PHYLite IP does not support core PLL reference clock connection. The PHYLite PLL reference clock must be connected to a dedicated reference clock pin.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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