Article ID: 000076850 Content Type: Troubleshooting Last Reviewed: 12/14/2022

Why does the PHY Lite for Parallel Interfaces for Intel® Arria® 10 FPGA IP fail simulation when the data configuration is set to “Differential”?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Software version 19.1, you may see simulation read errors when you set the data configuration to “Differential.”

    Resolution

    To work around these problems, open the *phylite_io_bufs.sv file under the altera_phylite_arch_nf_*\sim directory.

     

    Change the line from:

    assign group_data_out_n [grp_num][47 : GROUP_PIN_WIDTH[grp_num]-1]={(MAX_WIDTH-GROUP_PIN_WIDTH[grp_num]){1'b0}};

    to:

    assign group_data_out_n [grp_num][47 : GROUP_PIN_WIDTH[grp_num]]={(MAX_WIDTH-GROUP_PIN_WIDTH[grp_num] 1){1'b0}};

     

    This problem is fixed starting with the Intel® Quartus® Prime Software version 19.3.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs