Are there any known problems with the Intel® Stratix® 10 DDR4 Ping Pong PHY example design?

When using the Intel® Stratix® 10 EMIF IP in a DDR4 Ping Pong PHY configuration, there is a problem with the auto-generated example design if the Efficiency Monitor is enabled.

The Ping Pong PHY calibrates successfully, and the traffic generator test passes on the Ping PHY but fails with read data errors on the Pong PHY. This behavior is seen in both simulation and hardware operations.

Set the DDR4 IP parameter Diagnostics > Enable Efficiency Monitor to Disabled.

This problem is fixed in version 19.4 of the Intel® Quartus® Prime Pro Edition Software.