Yes, Quartus II timing analysis uses characterized package delays which are included in the device timing models.
The package delay number is incorporated in the CELL delay reported by the Quartus II timing analyzer. For example, the CELL delay for an input pin feeding a register is reported as follows by the Classic Timing Analyzer:
Info: Longest pin to register delay is 5.260 ns
Info: 1: IC(0.000 ns) CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AD24; Fanout = 2; PIN Node = 'd_in[1]'
Info: 2: IC(0.000 ns) CELL(3.260 ns) = 5.260 ns; Loc. = IOC_X0_Y25_N2; Fanout = 1; REG Node = 'outputreg'
Info: Total cell delay = 3.260 ns ( 100.00 % )
The CELL delay of 3.26 ns in the above example contains all I/O buffer, delay chain, and package delays.
The CELL delay for a register feeding an output pin is reported as follows:
Info: Longest register to pin delay is 5.420 ns
Info: 1: IC(0.000 ns) CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y1_N9; Fanout = 9; REG Node = 'inst4'
Info: 2: IC(2.916 ns) CELL(2.504 ns) = 5.420 ns; Loc. = PIN_H10; Fanout = 0; PIN Node = 'yvalid'
Info: Total cell delay = 2.504 ns ( 46.20 % )
Info: Total interconnect delay = 2.916 ns ( 53.80 % )
The CELL delay of 2.504 ns in the above example contains all I/O buffer, delay chain, and package delays.