Article ID: 000076831 Content Type: Troubleshooting Last Reviewed: 10/07/2020

Why does the E-Tile 100G Ethernet Dynamic Reconfiguration Design Example generation fail for both the Intel® Agilex™ and the Intel® Stratix® 10 devices?

Environment

  • Intel® Stratix® 10 DX FPGA
  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
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    Critical Issue

    Description

    Due to a problem with the Intel® Quartus® Prime Pro Edition Software version 20.1, the E-Tile Hard IP for Ethernet 100G Dynamic Reconfiguration Design Example generation will fail for both the Intel® Agilex™ and Intel® Stratix® 10 devices.

    Resolution

    No workaround for this problem exists in version 20.1 of the Intel® Quartus® Prime Pro Edition Software.

    This problem has been fixed starting in the version 20.2 release of the Intel® Quartus® Prime Pro Edition Software.

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