Article ID: 000076824 Content Type: Troubleshooting Last Reviewed: 07/20/2020

Why does the DisplayPort Intel® FPGA IP fail to output video when Vtotal of Main Stream Attribute (MSA) field is greater than 13-bit width?

Environment

    Intel® Quartus® Prime Standard Edition
    Intel® Quartus® Prime Pro Edition
    DisplayPort Intel® FPGA IP
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Critical Issue

Description

Due to a problem in version 14.0 and later of the Intel® Quartus® Prime software, the DisplayPort Intel® FPGA IP Pixel Clock Recovery Interface Hsync and Vsync signals stick low when the condition below is met:

  • Video resolution with Vtotal Main Stream Attribute (MSA) field exceeding 13-bit width or 8191 in decimal.
Resolution

This problem is fixed starting from the Intel® Quartus® Prime Pro Edition version 20.1 Software onwards.

Related Products

This article applies to 6 products

Intel® Cyclone® 10 GX FPGA
Stratix® V FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Cyclone® V FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs

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