Article ID: 000076799 Content Type: Troubleshooting Last Reviewed: 12/31/2022

Why do I see read, write and erase operation failure when using the OSC_CLK_1 for Intel® Stratix® 10 devices on Macronix flash?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

You will see the read, write and erase operation failure when the current design runs in the FPGA using OSC_CLK_1 as the configuration clock source on Marconix flash is larger than 128Mb.

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1.1. 

Related Products

This article applies to 2 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® FPGA Configuration Devices

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