Error (10198): Verilog HDL error at altpciexpav_stif_a2p_vartrans.v(145): part-select direction is opposite from prefix index direction
Error (10784): HDL error at altpciexpav_stif_a2p_vartrans.v(65): see declaration for object "AdTrWriteData_i"
Error (12152): Can't elaborate user hierarchy "fam_system_altera_pcie_a10_hip_170_qrwnsly:pcie_avmm_m|altpciexpav_stif_app:g_avmm.g_avmm.avalon_bridge|altpciexpav_stif_tx:tx|altpciexpav_stif_a2p_addrtrans:a2p_addr_trans|altpciexpav_stif_a2p_vartrans:vartrans"
Due to a limitation in the Intel® Arria® 10 FPGA Avalon® Memory Mapped PCIe Hard IP, you might encounter this error during compilation if the following parameters are selected in the Avalon Memory Mapped Settings:
- Avalon Memory Mapped address width set to 32-bit
- Size of address pages set to 4 GByte - 32 bits
You can set 64-bit in the Avalon Memory Mapped address width setting, then the address translation will not be required. Otherwise, you can set to 2 GByte - 31bits or lower in the size of address pages setting.
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.0.