What is the flow to modify the Intel® Stratix® 10 SoC Development Kit HPS DDR4 width and ECC configuration using the Golden Hardware Reference Design project as the starting point?

The Intel® Stratix® 10 SoC FPGAs can support the following HPS DDR4 configurations :

• 72 bits : 64 bit data 8 bit ECC
• 64 bits : 64 bit data
• 40 bits : 32 bit data 8 bit ECC
• 32 bits : 32 bit data
• 24 bits : 16 bit data 8 bit ECC
• 16 bits : 16 bit data

The Golden Hardware Reference Design (GHRD) project has an HPS DDR4 interface configuration with a width of 72 bits. The steps to modify the HPS DDR4 width and ECC configuration are shown below :

1)  Open the qsys_top.qsys file.

2)  Select the emif_hps component and open the parameter editor.

3)  Change the Memory tab > DQ width as required.

4)  If ECC isn’t required, unselect the Controller tab parameters > Enable Error Detection and Correction Logic with ECC and Enable Auto Error Correction to External Memory.

5)  Generate the qsys component.

6)  Open the top-level RTL file ghrd_s10_top.v

7)  At the top of ghrd_s10_top.v, change the inout wire bus width declarations for emif_hps_mem_mem_dbi_n, emif_hps_mem_mem_dq, emif_hps_mem_mem_dqs and emif_hps_mem_mem_dqs_n for your required DDR4 configuration.

8) In the Intel® Quartus® Prime Assignment editor or in the project .qsf file, make the following changes :

a) For the required DDR4 interface width, disable all the location assignments of the unused emif_hps_mem_mem_dbi_n, emif_hps_mem_mem_dqs, emif_hps_mem_mem_dqs_n and emif_hps_mem_mem_dq signals.

b) For narrower width interfaces with ECC, in order to meet the pin-out rules in the Intel Stratix® 10 SoC design guidelines and the Intel Stratix 10 EMIF IP User Guide HPS DQS group placements, the DQS group used for the ECC bits needs to move so it is placed in lane 3 of I/O bank 2M.

For a DDR4 interface width of 16 bit ECC, copy the pin locations for emif_hps_mem_mem_dbi_n[8], emif_hps_mem_mem_dqs[8], emif_hps_mem_mem_dqs_n[8], emif_hps_mem_mem_dq[71:64],  to emif_hps_mem_mem_dbi_n[2], emif_hps_mem_mem_dqs[2], emif_hps_mem_mem_dqs_n[2], emif_hps_mem_mem_dq[23:16] respectively.

For a DDR4 interface width of 32 bit ECC, copy the pin locations for emif_hps_mem_mem_dbi_n[8], emif_hps_mem_mem_dqs[8], emif_hps_mem_mem_dqs_n[8], emif_hps_mem_mem_dq[71:64],  to emif_hps_mem_mem_dbi_n[4], emif_hps_mem_mem_dqs[4], emif_hps_mem_mem_dqs_n[4], emif_hps_mem_mem_dq[39:32] respectively.

Additional information :

• Note the alert# pin is placed in DQS group 0 which is always in the project regardless of the HPS DDR4 interface width, and so no changes are needed.
• Further details for some configurations are shown in the Rocketboards article:  https://rocketboards.org/foswiki/Documentation/S10GSRDEnableHPS_DDR_ECC