Article ID: 000076744 Content Type: Troubleshooting Last Reviewed: 03/16/2018

Is there a known issue with Intel® Stratix® 10 3V IOs during configuration?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, due to a problem in Intel® Quartus® Prime Pro software versions 17.1 and earlier, 3V I/Os in Intel Stratix® 10 FPGAs may drive out a strong HIGH during configuration when the pins are assigned as outputs in your compiled design.

    This behaviour is not seen when the 3V I/Os are assigned as inputs or bidirectional IOs.

    These 3V I/Os are located in I/O banks 6A,6B,6C,7A,7B,7C and are available in different density and package variants of Intel Stratix 10 devices.

    Resolution

    This  problem is scheduled to be fixed in a future release of the Quartus Prime Pro software.

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