Why does the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example simulation run hang?

Due to a problem in the Intel® Quartus® Prime Pro Edition version 20.1 Software, the design example generated by the 25G Ethernet Intel® Stratix® 10
FPGA IP with dynamic reconfiguration and PTP enabled, will hang when simulated with either Synopsys* VCS* simulator or Cadence* Xcelium*/NCSIM* simulator. 

To avoid this problem, user is encounraged to use Mentor* Modelsim* simulator to simulate the design example.

This problem is fixed starting from the Intel® Quartus® Prime Pro Edition v20.3 software onwards.