Why is there a significant link up delay difference between Serial Lite III Streaming Intel® FPGA IP instances in simulation?

Due to the reset staggering feature of the Intel® Stratix® 10 L-Tile transceivers and H-Tile transceivers, you may observe significant link up delay difference between Serial Lite III Streaming Intel® FPGA IP instances in simulation. 

To work around this effect in simulation, change the following in the <ip instance phy top>.v under the sim folder:

    From 

        .reduced_reset_sim_time          (0),

    To

        .reduced_reset_sim_time          (1),

An example of the <ip instance phy top> .v file is shown below:

        altera_sl3_tx\altera_sl3_phy_top_181\sim\altera_sl3_tx_altera_sl3_phy_top_181_jl2kkei.v

#Note that this modification reduces the link up time in simulation only.

This is the expected behaviour and will not be changed in any future release of the Intel® Quartus® Prime software.