Article ID: 000076727 Content Type: Troubleshooting Last Reviewed: 01/17/2020

Why do the design examples for the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps variants send an incorrect number of packets?

Environment

    Intel® Quartus® Prime Pro Edition
    Ethernet
    25G Ethernet Intel® FPGA IP
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Description

When using the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, when creating a design example with the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps base variants, operating in fixed and incremental modes send an incorrect number of packets. 

Resolution

To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, stop the running project and restart the device.

This problem has been fixed starting in the Intel® Quartus® Prime Pro edition software version 19.3.

Related Products

This article applies to 4 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 TX FPGA
Intel® Stratix® 10 DX FPGA

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