Critical Issue
Description
If you generate a RapidIO IP core instance in Qsys, and specify output language VHDL, your RapidIO IP core cannot simulate successfully with the Aldec Riviera-PRO simulator.
Also refer to RapidIO IP Core Variations With an Avalon-MM Slave Module Fail in VHDL Qsys Systems.
Resolution
This issue has no workaround. You can simulate the IP core with the Mentor Graphics ModelSim simulator, the Cadence NCSIM simulator, or the Synopsys VCS-MX simulator, instead.
This issue will be fixed in a future version of the RapidIO IP core.