Article ID: 000076715 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Can I use the reset sequence recommended by Altera® for PIPE mode also?

Environment

  • Stratix® II GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, a modified reset sequence shown below should be used for the PIPE  mode for the following reasons.

  • As per the PIPE interface specification, the link layer expects transitions in the ‘pipephydonestatus’’ signal from the PIPE interface to complete the compliance testing phase during link initialization.
  • The ‘‘pipephydonestatus’ signal from the PIPE interface becomes active only after the rx_digitalreset is DE-asserted.
  • the reset controller that controls the resets looks for ‘rx_freqlocked’ from the GXB to go high to de-assert rx_digitalreset.
  • During the compliance testing phase the ‘rx_freqlocked’ does not go high because of not receiving continuous valid data. Therefore the compliance testing phase cannot be completed with this reset mechanism because of the above reasons.

To overcome this problem, the reset controller code should be modified to look for rx_pll_locked from the GXB to go high to deassert rx_digitalreset.

 

 

Figure 1. PLL Waveforms

Figure 1
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