No, Stratix® series devices do not support asynchronous memory. Altera® recommends using synchronous memory blocks for Altera designs.
Stratix series devices do support a pseudo-asynchronous read where the output data is available during the clock cycle when the read address is driven into it. Pseudo-asynchronous reading is possible in the simple and true dual-port modes of the Stratix and Stratix II M512 and M4K blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers.
For more information about converting asynchronous memory designs, refer to AN 210: Converting Memory from Asynchronous to Synchronous for Stratix and Stratix GX Designs (PDF).