Article ID: 000076680 Content Type: Troubleshooting Last Reviewed: 06/16/2017

What is the signal description for the rxm_irq port when using the Stratix 10 Avalon-MM mode of the PCI Express Hard IP core?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a mistake in the 2017.05.08 revision of the Intel® Stratix® 10 Avalon®-MM Interface for PCIe® Solutions User Guide, the rxm_irq port descrtiption is missing.

    Resolution

    The following information will be added to the next update of the documentaiton:

    Connects Qsys interrupts to the Avalon-MM interface. This signal is only available for the Avalon-MM when the CRA port is enabled. A rising edge triggers an MSI interrupt. The hard IP core converts this event to an MSI interrupt and sends it to the Root Port. The host reads the Interrupt Status register to retrieve the interrupt vector. Host software services the interrupt and notifies the target upon completion.


    Qsys-generated variations have as many as 16 individual interrupt signals (<m>≤15). If rxm_irq_<n>[<m>:0] is asserted on consecutive cycles without the deassertion of all interrupt inputs, no MSI message is sent for subsequent interrupts. To avoid losing interrupts, software must ensure that all interrupt sources are cleared for each MSI message received.

    Related Products

    This article applies to 3 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 SX SoC FPGA

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