Article ID: 000076679 Content Type: Troubleshooting Last Reviewed: 05/05/2021

Why does the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* Design Example error during simulation if the debug toolkit is enabled?

Environment

  • Intel® Stratix® 10 DX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.1 or earlier, Intel® P-Tile Avalon® Memory Mapped Hard IP for PCI Express* Example Design with enabling debug toolkit feature reports error during simulation.

    Error-[CFCILFBI] Cannot find cell in liblist  ./../..//../../../pcie_ed/sim//../../ip/pcie_ed/pcie_ed_dut/sim//../intel_pcie_ptile_ast_200/sim/ptile_debug_toolkit/ptile_debug_toolkit.sv, 285

    Resolution

    To work around this problem, disable the debug toolkit feature when generating the simulation environment.

    The Intel® FPGA P-Tile Avalon® Memory Mapped IP for PCI Express* User Guide is scheduled to be updated to detail this restriction.

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