Article ID: 000076677 Content Type: Troubleshooting Last Reviewed: 10/07/2020

Is the Ready Latency parameter supported when using the E-Tile Hard IP for Ethernet Intel® FPGA IP Core in 100G mode with PTP enabled?

Environment

  • Intel® Stratix® 10 DX FPGA
  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
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    Critical Issue

    Description

    Due to a bug in the Intel® Quartus® Prime Pro Edition software the E-Tile Hard IP for Ethernet Intel® FPGA IP Core in 100G mode incorrectly allows the Ready Latency parameter to be selected when PTP mode is enabled.
    The Ready Latency parameter is not supported in the E-Tile Hard IP for Ethernet Intel® FPGA IP Core in 100G mode if PTP is enabled?

    When using the E-Tile Hard IP for Ethernet Intel® FPGA IP Core in 100G mode with PTP enabled, the Ready Latency is fixed at zero.

    Resolution

    No workaround for this problem exists.

    This problem has been fixed starting with the v20.2 release of the Intel® Quartus® Prime Pro Edition software by removing the Ready Latency parameter from the IP GUI when PTP mode is selected.

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