Article ID: 000076675 Content Type: Troubleshooting Last Reviewed: 12/14/2022

Why does the simulation of the eSRAM Intel® FPGA IP targeting the Intel® Stratix® 10 using Mentor* ModelSim* show incorrect read data?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When simulating the eSRAM Intel® FPGA IP targetting the Intel® Stratix® 10 devices with Mentor* ModelSim*, you may observe incorrect read data due to incorrect simulation options.

    Resolution

    To work around this problem, add the option below in the msim_setup.tcl file:

    set USER_DEFINED_VERILOG_COMPILE_OPTIONS "+define+ESRAM_SIM"

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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