Article ID: 000076674 Content Type: Troubleshooting Last Reviewed: 11/20/2020

What is the correct clock to use for the application clock domain when using the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express*?

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 DX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    The p<n>_app_clk (where n=1,2,3,4) is the correct clock to use as the application clock for the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express*. The Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* User Guide revision UG-20237 | 2020.11.17, incorrectly refers to coreclkout_hip as the application clock. Similarly the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* currently generates a top level coreclkout_hip port which should not be used as the application clock.

    Resolution

    The Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* User Guide and the IP top level RTL are scheduled to be updated in the future release of the document and the IP.

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