Article ID: 000076672 Content Type: Troubleshooting Last Reviewed: 02/03/2020

Why does the Low Latency Ethernet 10G MAC Intel® FPGA IP generated design example simulation fail?

Environment

  • Intel® Cyclone® 10 GX FPGA
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
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    Critical Issue

    Description

    Due to a problem with the Intel® Quartus® Prime Pro software version 19.3, the Low Latency 10G MAC Intel® FPGA IP generated design example may encounter the above problem. This is because the simulation model outputs an "X" (undefined) instead of valid data,  this causes the block lock signal to de-assert and the simulation then stops. 

    Resolution

    This problem has been fixed starting in the Intel® Quartus® Prime Pro Edition software version 19.4.

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