Article ID: 000076647 Content Type: Product Information & Documentation Last Reviewed: 04/04/2017

How do I resolve Arria 10 External Memory Interfaces DDR4 IP read capture timing violations ?


  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP

    When a correctly parameterized Arria® 10 DDR4 interface is configured for a 1200MHz memory clock frequency in a -1 speed grade Arria 10 FPGA device, some configurations may show small Read Capture timing violations in TimeQuest Report DDR.


    Here are some techniques to improve Read Capture timing margins. These are applicable for any DDR4 IP configuration and not just for 1200MHz operation.

    1) Read DBI : Select the DDR4 IP Memory Tab Read DBI parameter option. Ensure you also select the correct Memory CAS latency setting parameter for Read DBI from the DDR4 memory device data sheet speed bin table for your configuration and operating frequency.

    2) DQS Group skew : Reduce the value of the Maximum system skew within DQS group under the DDR4 IP Board tab. The default is set to 20ps but lower skews are achievable with careful PCB layout.

    3) Use a faster speed grade DDR4 memory device.

    4) Periodic OCT Recalibration : Operate the DDR4 memory IP in a configuration where periodic OCT recalibration is supported. Refer to the Parameterization message window in the QSYS parameter editor and there will be a message to indicate if Periodic OCT recalibration is enabled.

    Not all DDR4 configurations support this feature. Note that if Periodic OCT recalibration is enabled, it prevents the user application from accessing the DDR4 memory for a short period of time when the recalibration occurs.
    For further information refer to the Periodic OCT Recalibration section in Chapter 2 of the EMIF Handbook Volume 3 where it shows how to calculate this delay.

    In the DDR4 memory presets, the default configuration causes Periodic OCT recalibration to be disabled. To enable it:

    • Deselect the FPGA I/O tab parameter Use default I/O settings.
    • For Address/Command and Memory Clock, change the I/O standard to SSTL-12 Class I and set the Output Mode to be a Current Strength.

    Perform board level simulations to optimze the signal integrity, drive strength and terminations for your interface.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs



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