The fitting error occurs because the Triple Speed Ethernet’s transceiver-reset-sequence logic is clocked by a reference clock and the Cyclone® IV GX FPGA's dedicated reference clock for transceivers cannot be routed to the global clock network.
The following patch provides a solution to ensure that fitting error does not occur in Cyclone IV GX devices due to global clock network limitation.
Download the following Quartus® II software version 10.1SP1 patch 1.77:
- Quartus II software version 10.1SP1 patch 1.77 for Windows
- Quartus II software version 10.1SP1 patch 1.77 for Linux
- Quartus II software version 10.1SP1 ReadMe for patch 1.77
Caution:
You must either have installed the Quartus II software v10.1 SP1 previously or install the Quartus II software v10.1 SP1 before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.
After you have installed the patch, regenerate your Triple Speed Ethernet Intel® FPGA IP before you compile your design.