Article ID: 000076636 Content Type: Troubleshooting Last Reviewed: 05/19/2017

Why do my non-posted TLPs not appear on the receive AVST interface?

Environment

    PCI Express
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

As described in the user guides for the Hard IP for PCI Express* Avalon-ST Interface, the rx_st_mask input will stall all non-posted TLPs when asserted.

Resolution

To work around this issue, ensure that the rx_st_mask input is deasserted when you wish to receive non-posted TLPs on the AVST Rx interface.

Related Products

This article applies to 12 products

Stratix® V FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Stratix® IV GX FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs
Arria® II FPGAs
Cyclone® IV GX FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Stratix® IV GT FPGA

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