Article ID: 000076629 Content Type: Troubleshooting Last Reviewed: 07/26/2017

Why is the IRQ_HPD of the DisplayPort IP Core asserted before link training?

Environment

    Intel® Quartus® Prime Pro Edition
    DisplayPort Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The DisplayPort IP Core Sink may assert CR_Lock before link training, and the pseudo CR_Lock generates pseudo IRQ_HPD before link training. Because CR_Lock and IRQ_HPD are supposed to be valid only during and after link training, the DisplayPort Source should ignore the pseudo IRQ_HPD.

 

Resolution

This problem is scheduled to be fixed in a future release of the Quartus® Prime software.

Related Products

This article applies to 4 products

Cyclone® V FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs
Stratix® V FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs

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