Article ID: 000076625 Content Type: Troubleshooting Last Reviewed: 04/08/2020

Why does the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps design examples send an incorrect number of packets?

Environment

  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 DX FPGA
  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps design examples operating in both fixed mode and increment mode transmit an incorrect number of packets. The observed transmit pattern shows that the IP is only sending half the number of expected packets. 

    Resolution

    This problem has been fixed starting in version 19.3 of the Intel® Quartus® Prime Pro edition software.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.