Article ID: 000076625 Content Type: Troubleshooting Last Reviewed: 04/08/2020

Why does the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps design examples send an incorrect number of packets?

Environment

    Intel® Quartus® Prime Pro Edition
    25G Ethernet Intel® FPGA IP
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Description

When using the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps design examples operating in both fixed mode and increment mode transmit an incorrect number of packets. The observed transmit pattern shows that the IP is only sending half the number of expected packets. 

Resolution

This problem has been fixed starting in version 19.3 of the Intel® Quartus® Prime Pro edition software.

Related Products

This article applies to 4 products

Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 TX FPGA
Intel® Stratix® 10 DX FPGA
Intel Agilex® 7 FPGAs and SoC FPGAs F-Series

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